1. Field of the Invention
The present invention relates to a structure of a field effect transistor making use of two-dimensional electron gas formed in a hetero-junction interface as an active layer (2DEGFET) and more particularly to a field effect transistor having an epitaxial layer structure which enables to enhance its performance.
2. Description of the Prior Art
An example of conventional 2DEGFET devices is shown in the attached FIG. 5 by a sectional view. Such 2DEGFET is reported for example in IEEE Electron Device Letters, Vol. EDL-7, No. 12 (1986), p 649 by Henderson, et al. In the FIG. 5, 1 denotes a semi-insulating (S.I.) GaAs substrate, 2 denotes a non-doped GaAs layer constituting a buffer layer, 3 denotes a channel layer comprising non-doped InGaAs and 4 denotes a carrier supplying layer constituted by an n-type AlGaAs layer. In the InGaAs layer 3, two-dimensional electron gas (2DEG) is induced to form a channel layer in the vicinity of the interface with the AlGaAs layer 4. On the AlGaAs layer 4, a cap layer 6 comprising an n-type GaAs is formed and, on this cap layer 6, a source electrode 7a and a drain electrode 7b are formed by evaporation to produce an ohmic contact with the 2DEG channel layer. Further, a gate electrode 8 is formed at a recess portion formed across the cap layer 6.
Heretofore, improvements of performances of 2DEGFET have been carried out mainly by shortening gate length and modififying construction of the epitaxial layer, but they now achieves maximum from the technical point of view. At present, essential problem for realizing low-noise and high-gain devices is how to reduce a parasitic resistance in a source electrode or a gate electrode.
Potential diagram of a conduction band in a hetero-interface X.sub.5 -Y.sub.5 between the cap layer and the channel layer of 2DEGFET shown in FIG. 5 is shown in FIG. 6, from which it is understood that a path for electron flow is formed also in the cap layer 6 in parallel to the 2DEG channel layer 3. It is known that this second current path in the cap layer works as a bypass of the 2DEG channel layer and contributes to reduce the parasitic resistance of the device. The channel layer 3 and the cap layer 6 are connected by a tunnel current flowing through the AlGaAs layer 4. It is therefore considered that in such 2DEGFET, a source resistance is determined by a sheet resistance of the cap layer, a tunnel resistance, a sheet resistance of the channel layer and a contact resistance in the electrode portions. As long as 2DEG is used as a carrier, there is naturally a limitation to reduction of the sheet resistance of the channel layer. Further, the tunnel resistance and the contact resistance are considered to be determined by height of a potential barrier and so their control is not easy. On the other hand, the sheet resistance of the cap layer can easily be reduced by increasing a sheet electron density in the cap layer. Therefore, it has been tried to reduce the source resistance by increasing the thickness of the high density cap layer, up to now. In compound semiconductors having a small state density in a conductive band, however, there is naturally a limitation to the increase of the carrier density and, for example, in a case of GaAs, the carrier density reaches saturation at an extent of 5.times.10.sup.18 /cm.sup.3. There is a limitation also to the thickness of the cap layer, since too thick cap layer will soon lose its good contact. As mentioned above, it has been difficult to sufficiently reduce the sheet resistance in the cap layer by the prior art.